Continuous-time (CT) zoom analog-to-digital converters (ADCs) are highly efficient for high-resolution applications but typically suffer from DAC mismatch errors or require complex digital calibration. This talk presents advanced CT zoom ADC architectures that achieve state-of-the-art energy efficiency and high resolution by utilizing advanced filtering to ensure high linearity without explicit calibration. We focus on key innovations that address conventional trade-offs: Interstage Low-Pass and FIR Filtering, and Robust Mismatch Error Shaping (MES). Silicon prototypes fabricated in 28-nm and 65-nm CMOS demonstrate excellent performance, achieving an SFDR of up to 105.7 dB and a Schreier FoM exceeding 180 dB across bandwidths from 50 kHz to 1 MHz. This talk will cover the theory, architectural trade-offs, and practical design techniques of these highly efficient, filtering-assisted CT zoom ADCs.